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LPD6803 datasheet 1 general general general general description: description: description: description: LPD6803 is a 3 channel constant-current driver and grey-level modulate output , it uses advanced high-voltage cmos technology, provide 3-way, designed to meet the needs of driving function in the led lighting system, especially in the dissociation with m utual grey level in the full-colour lighting system.. LPD6803 includes serial shift register and concatenation driver circuit, grey level data shift into serial shift register in the clock, and transfer saving , it transfer to interface 3 after pulse-width modulate ,then output, serial shift register and grey-level counter can be controlled by different clock si gnal. i n the meantime, LPD6803 driver data signal and control signal , and output next circuit. features: features: features: features: 3channel driver output, maxim current per channel is 45ma, led light voltage can reach 12v. output adopt in-rush online feedback contant-current driver structure, compatible with constant-voltage module, it also can contact outside equipment and transfer to higher voltage or current output driver. built-in ldo voltage-stabilizing circuit, voltage range is 3-8v, and have 5v stabilizing voltage output. a dopt self-add token-ring technology dual shift line, shift clock can reah 24mhz. directly input grey-level data, it is transfer to 256 output with reverse-gamma regulator after inside super-pwm technology, e.g, adopt built-in oscialator as grey- level clock, it support free-run module output, especially can be used in low-cost controller. d ata clock signal is drived strongly to next chip to enhance level after built-in phase- lock circuit. h igh-voltage cmos technology, industrial design, with extra-good interference immunity w ith sop16/qfn16 pb-free package, meet the requirement of rohs , also can provide cob package or die. f f f f ootprint: ootprint: ootprint: ootprint:
LPD6803 datasheet 2 LPD6803 LPD6803 LPD6803 LPD6803 footprint footprint footprint footprint function function function function description description description description : : : : function function function function block: block: block: block: foot name function 1 din serial data input, built-in voltage pull- up 2 gmode grey-level regulate mode: gmode=1,adapt line modulate,gmode=0,adapt re-gama 256 grade non-line regulate,built-in voltage pull-up 3 omode control output polarity: omode=1, output is in-constant current/voltage drive mode,cmode=0, output is out drive mode,voltage built-in pull-up 13 cmode choose inside grey clock gclk, cmode=0, gclk=dclk, cmode=1, gclk= inside oscillator output, built-in pull-up 4 dclk serial data clock input, built-in pull-up 5,7,11 out1,out2,out3 3-way driver output 6,8,10 fb1,fb2,fb3 feedback input in constant current state 15 dout serial data output, after inside strongly drive 12 dclk0 serial clock output, after inside pll and strongly drive 16 vcc ldo power, range is 4.5v---8v 14 vout when vcc>5v, 5v stable voltage output, when vcc<5v, vout=vcc, can be used as inside working voltage, suggest outside contact a 0.01uf----0.1uf capacity 9 gnd ground
LPD6803 datasheet 3 i nput dealing ldo ower dealing super-pwm non-line adjust module o scillator basic counter c ounter compare array s hift register array o utput driver o utput driver o utput driver o utput re- gernate driver vout output feedback output feedback output feedback dout dclko basic basic basic basic timing timing timing timing sequence sequence sequence sequence a. first shift in 32bit 0 as start frame, then shift in all data frame, start frame and data frame both are shift by high-bit, every data is input on dclk rising edge. b. t he first data frame is corresponding led light nearest from shift-in polar, its format includes 1bit as start 1 plus 3 groups 5bits grey level. c. t urn shift in all data, add append pulse of corresponding point, new data start valid. f f f f unction unction unction unction features: features: features: features: limited parameter: parameter symbol range unit supply voltage vdd 3-8 v led light voltage vled 3-12 v data clock frequency fclk 25(compatible with grey level at 10) mhz maxim driver current iomax 45 at constant voltage, 30 at constant current ma channel current error dio chip inside <5%, between chip <6% % power consumption pdmax 600 mw
LPD6803 datasheet 4 suggested working parameter: t iming iming iming iming sequence sequence sequence sequence parameter parameter parameter parameter typical typical typical typical application application application application circuit: circuit: circuit: circuit: > inside inside inside inside constant constant constant constant voltage voltage voltage voltage driver driver driver driver (compatible (compatible (compatible (compatible with with with with zql9712) zql9712) zql9712) zql9712) mode: mode: mode: mode: soldering temp tm 300(8s) working temp top -40 ---+80 saving temp tst -65 ---+120 parameter symbols range unit supply voltage vdd 5-7.5 v voltage-stabilizing output voltage vout 5 5% (customer data) v input voltage vin -0.4 vout+0.4 v data clock frequency fclk 0-15 mhz clock high-level voltage width tclkh >30 ns clock low-level voltage width tclkl >30 ns data build time tsetup >10 ns data keep time thold >5 ns power comsumption pd <350 mw working temp top -30 +60 t iming sequence parameter:(t=25 ,vdd=5v, omode=1,gmode=0,cmode=1) parameter symbols testing condition range unit maxim up and down time tr vdd=5v <500 ns of innput signal tf <400 up and down time of ttlh cl=30pf,rl=1k <15 ns concatenation output signal tthl <15 maxim delay time of tpd cl=30pf,rl=1k <12 ns concatenation output tco <12 min pwm width of driver output tonmin iout=20ma 200 ns maxim open and close time ton iout=20ma <80 ns of driver output signal toff <80
LPD6803 datasheet 5 this mode (omode=high voltage level or dangle)is suitable used in the situation which vdd not higher 12v and current on each way not huge 400ma, if vdd<7.5v, you can ignore those parts in blue dashed above chart, directly contact vdd to vcc. current regulator resistance count: rl=(vdd-vled-vout)/iled here: rl is limit current resistance value, vdd is led light supply voltage, vled is led light voltage when it breakover, vout is saturation voltage of the output polar to the grand(about 0.4v C 0.8v), iled is led working current( normally no bigger 20ma) LPD6803 has strong driver capability , in the many led apply situation, we can adopt the contact of f irst serial then parallel ( see right chart), but we must pay attention on power consumption can not exceed maxim value pdmax: pd=iled1*vout1+iled2*vout@+iled3*vout3+pic here : pic is ic basic power consumption , normally not exceed 25mw. >inside >inside >inside >inside constant constant constant constant current current current current driver driver driver driver mode: mode: mode: mode:
LPD6803 datasheet 6 t h is mode (omode=high level or dangle) application is same as above , only add a rx at fbx polar which regulate current, this led current is decided by rx: iled 0.7v/rx c hart1: iled C rx curve pls note that only can keep constant current when voltage to the grand vout is at the range of 1.1---6v. that is meet: vled+6v+iled*rl R vdd R vled+1.1v+iled*rl circuit value must notice that power consumption pd won t exceed its maxim value pdmax. pd=iled1*(vout1-0.7v)+iled2*(vout2-0.7v)+iled3*(vout3-0.7v)+pic here iled1/iled2/iled3 is respectively current which passed each led light, and vout1/vout2/vout3 is respectively each output voltage to the grand .
LPD6803 datasheet 7 rl is normally tens ohm, no any effect to iled, it is ok if no rl, but a suitable rl can be help to share chip power consumption pd, can improve working stability. ? ? ? ? outside constant voltage drive mode: this mode (omode=grand)is suitable in many leds situation or high light voltage , a ctually, serials leds are drived by outx which control npn transistor whish is outside contact to . limited current resistance count: rl=(vdd-vled-vce)/20ma here transistor works in switch area, vce is saturate voltage of transistor, normally is 0.5v---0.8v, base resistance rb can be set at 2k 5k, other signal contact mode are same as prior mode. t his mode often is used in multiple way first serial then parallel connection, because all leds won t light on this once any led switch off in serial route, s o we must obey this connection rule: led qty can not be too many in serial route (normally 3-6pcs), and can not be too less in parallel route. this can reduce a ccidents influence of one broken led, and will make limited resistance to zero , m ake one huge power resistance to many small power ones, make central installation to disperse one, it is good to conduct heat and make lights more compaction. o utside constant current drive mode:
LPD6803 datasheet 8 t his mode (omode=high level voltage or dangle) is suitable in several leds and vdd is higher than 12v, its essence is to higher capability of withstand voltage in the time of keeping characteristic of constant current in the circuit. c urrent passed led : iled= io* /( +1) h ere io is current value related to chart 1, transistor is working in amplify area, is amplify multiple, when is bigger, above formula can be near equal to : iled = io (bias resistance rb can be get as 5k) h ighest capability of withstand voltage vdd is decided by vceo on npn transistor, normally is 25v or above. linking signal driver and link: c onsidering of that the distance between of chips may be long long, dout and dclko o utput terminal is designed to push-pull strong drive circuit, after testing, it can drive 6meters length signal line when clock is 2m, to prevent signal echo, normally, pls serial a 50 resistance at dout and dclko, then output to next step. control circuit and software reference design: v ia set cmode, LPD6803 grey level counter can adapt dclk as clock( cmode=0), a lso can adapt built-in 1.2m(error 15%)osscilator output of as clock(cmode=1 o r dangle), prior one is normally used in those based on cpld/fpga high cost control system, later one is often used in low cost mcu control system. i n cmode=1 mode, mcu write display data into chip via spi or two gpio interface line, then each chip will automatically produce drive output with related duty cycle according to input grey level value, after data transfered, mcu can deal with
LPD6803 datasheet 9 other task, during this time, each LPD6803 will continue keeping original duty cycle drive output(free-run mode), till mcu send out next updated data. n otice: after all data are input in chip on the up-edge of dclk, it may need send more dclk pulse (din=0), on principle, how many group point in the transfer link, how many related pulse need to be sent out, it is important to which later chip built-in pll re-gernate circuit can work in gear. t o make LPD6803 produce more particularity grey level by less data, when gmode=0/ cmode=0, built-in super-pwm can change 5 bit data into non-line 256 grade grey output, minimum open width is 1t, maxim open width is 256t ( t is grey clock cycle) w hen gmode=1 or dangle , output is line 32 grade grey, minimum open width is 4t , and maxim open width is 128t. c51 example: //sdo, sclk is data and shift output, bit variability ,ndots is light qty // this program is only suitable in gmode=1,cmode=1 situation. // first output 32 0 start frame sclk=0; sd0=0, f or (i=0;i<32;i++){sclk=1;sclk=0; } // then output ndots data, here suppose each point colour are(dr,dg,db) //dr,db,dg is red, green and blue grey level 0-31 f or (i=o;i>=1; } // output 5 bits green data m ask=0x10; f or (j=0;j<5;j++) { if(mask &dg)sd0=1; e lse sd0=0; sclk=1;sclk=0; m ask>>=1; }
LPD6803 datasheet 10 //output 5bits blue data m ask=0x10; f or (j=0;j<5;j++) { if(mask & db) sd0=1; e lse sd0=0; sclk=1;sclk=0; m ask>>=1; } } // after output all ndots data, need add ndots pulse sd0=0; f or (i=0;iLPD6803 duty cycle table: input data output duty cycle (unit: 1/256) 0 0 1 1 2 3 3 5 4 8 5 12 6 16 7 21 8 26 9 32 10 38 11 45 12 52 13 60 14 68 15 76 16 85 17 95 18 105 19 115 20 125 21 136 22 148
LPD6803 datasheet 11 m emo: this table is output duty cycle related to 32 grade grey level when gmode=0, i ts data is revised curve related to gamma=1.8 sop16 package dimension: 23 160 24 172 25 185 26 198 27 211 28 225 29 239 30 254 31 256
LPD6803 datasheet 12 qfn16 package dimension:
LPD6803 datasheet 13

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